Post-Quantum Cryptography Hardware IP Cores
We develop and license Post-Quantum Cryptography (PQC) Hardware IP cores, pioneering device security to ensure your data and infrastructure are protected against emerging quantum threats.
Our implementations are engineered for constrained environments — minimising LUT footprint, RAM usage, and power consumption without compromising compliance or security. Designed for IoT, embedded, and edge devices where resources are limited and efficiency is critical.
Migration to Post-Quantum Cryptography is Certain
In the dawn of the quantum computing era, the integrity of internet encryption is under imminent threat.
Data harvested today will be at risk tomorrow. The urgency to adopt PQC standards is a present necessity.
U.S. government entities and European agencies are rapidly moving towards PQC mandates. Vicip is your proactive defense.
PQC security that fits your hardware
Many devices cannot afford the resource overhead of conventional PQC implementations. Vicip IP cores are built from the ground up for low-power, low-resource targets — minimal BRAM usage and a small LUT footprint across all our products.
Implement next generation cryptography standards
Protect your systems from both current and future threats with Vicip's verified PQC Intellectual Property.
Embed our hardware solution across industries
Our PQC IPs provide next-generation, quantum-resilient security for sensitive environments.
VIC-ML-KEM-X (FIPS 203) Key Encapsulation IP Core — Fully Validated
Our flexible VIC-ML-KEM-X hardware accelerator is production-ready, fully compliant with the definitive FIPS 203 standard, and 100% ACVP verified across all execution blocks. The monolithic public-key subsystem supports ML-KEM-1024, ML-KEM-768, and ML-KEM-512, available in five pre-synthesis configurations: standalone, area-optimized 512-only, 768-only, or 1024-only engines, or dynamic multi-mode cores — dual-mode (768/512) or tri-mode (1024/768/512) — switchable on the fly via APB register controls. All variants operate comfortably within high-frequency clock domains and feature low-overhead physical defenses — including 2-share Boolean comparison masking, randomized coefficient execution shuffling, and dynamic PRNG state-mixing — to safely eliminate localized Side-Channel Analysis (SCA) leakage profiles without sacrificing silicon efficiency.
ML-DSA Hardware Development Underway
Vicip has completed the RTL implementation of the ML-DSA Key Generation function for the ML-DSA-44 parameter set (k=l=4), with validation against 25 ACVP test cases.
This marks the beginning of Vicip's ML-DSA hardware implementation, with development now progressing toward the substantially larger ML-DSA signing architecture.
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Secure your quantum-safe future with Vicip.